Modeling of chemical mechanical polishing for shallow trench isolation

Chemical mechanical polishing (CMP) is a key process enabling shallow trench isolation (STI), which is used in current integrated circuit manufacturing processes to achieve device isolation. Excessive dishing and erosion in STI CMP processes, however, create device yield concerns. This thesis proposes characterization and modeling techniques to address a variety of concerns in STI CMP. Three major contributions of this work are: characterization and modeling of STI CMP processes, both conventional and nonconventional; layout optimization to reduce pattern-dependent dishing and erosion; and modeling of wafer nanotopography impact on STI CMP yield. An STI CMP characterization method is combined with a chip-scale pattern-dependent model to create a methodology that enables tuning of STI CMP process models and prediction of post-CMP dishing, erosion, and clearing times on arbitrary layouts. Model extensions enable characterization of STI CMP processes that use nonconventional consumable sets, including fixed abrasive pads and high-selectivity silica-based and ceria-based slurries. Experimental data validates the accuracy of the model for both conventional and nonconventional processes. Layout optimization techniques are developed that reduce pattern-density dependent dishing and erosion. Layout design modification is achieved through the use of dummy STI active areas and selective reverse etchback structures. Smart algorithms allow for optimal density distributions across the layout. The effect of wafer nanotopography (height variations that exist on unpatterned silicon wafers) is explored, characterized, and modelled. A diagnostic tool for examining the impact of nanotopography on STI device yields is developed, based on contact wear modeling. An aggregate estimator for the combined effect of wafer-scale nanotopography and chip-scale pattern-dependent dishing and erosion is developed. The techniques developed in this thesis can be used both for process optimization and for diagnosis and correction of potential problems due to layout, wafer and CMP process interaction. The characterization and modeling methods create a comprehensive set of tools for process characterization and post-CMP erosion and dishing prediction in STI processes. Thesis Supervisor: Duane S. Boning Title: Associate Professor of Electrical Engineering and Computer Science